;DG75 Clock - 4-digit clock using Japanese-style 9-segment displays
;ATtiny214 @ 2 MHz (internal osc.) + 32 KiHz backup crystal
;Fuses: factory defaults
;
;PORTS
;  PA0   = [UPDI] / Debug output (needs FUSE[5] = 0xC0 for GPIO + 12V UPDI)
;  PA1   = Colon (active low)
;  PA2   = Segment shift register clock
;  PA3   = Segment shift register data / Segment i
;  PA4   = Digit 1 (left)
;  PA5   = Digit 2
;  PA6   = Digit 3
;  PA7   = Digit 4 (right)
;  PB0   = mains frequency input (50 Hz or 60 Hz)
;  PB1   = Push button (active low, int. pull-up)
;  PB2-3 = [32 KiHz XTAL]
;
;SHIFT REGISTER
;  DATA IN            = Segment i
;  Q1 (shifted last)  = Segment h
;  Q2                 = Segment g
;  Q3                 = Segment f
;  Q4                 = Segment e
;  Q5                 = Segment d
;  Q6                 = Segment c
;  Q7                 = Segment b
;  Q8 (shifted first) = Segment a
;
;DISPLAY
;    aaaaaaa
;   a   h   b
;  f   hh   b
;  f    h  b
;   f   h b
;    fff b gg
;     e cc
;    e i  c
;   e  i   c
;  e   i   c
;  d   i   d
;   ddddddd
;
;VERSIONS
;  2024-08-11  Arne Rossius
;   * first version

.include "../include/tn214def.inc"

.undef	XL
.undef	XH
.undef	YL
.undef	YH

;R1:R0 = multiplication result (used in interrupt)
.def	dim_cnt = R2
.def	ac_restore_cnt = R3
.def	last_ac_l = R4
.def	last_ac_h = R5
.def	zero = R6
.def	mux = R7
.def	intdiv = R8
.def	sreg_backup = R9
.def	digit1 = R10
.def	digit2 = R11
.def	digit3 = R12
.def	digit4 = R13
.def	set_timeoutL = R14
.def	set_timeoutH = R15

.def	temp = R16
.def	temp2 = R17
.def	count = R18
.def	subsec = R19
.def	second = R20
.def	minute = R21
.def	hour = R22
.def	button_cnt = R23
.def	inttmp = R24
.def	inttmp2 = R25
.def	timeout = R26
.def	set_digit = R27
.def	flash = R28
.def	flags = R29
	.equ	fButtonShort = 0
	.equ	fButtonLong = 1
	.equ	fTimeSet = 2
	.equ	fAcState = 3
	.equ	fAcFailDetected = 4
	.equ	fAcEdgesDetected = 5
	.equ	fAcRestored = 6
	.equ	fDST = 7

;R31:R30 used for Z pointer

;user settings
.equ	F_MAINS = 50 ;mains frequency (time base): 50 Hz or 60 Hz
.equ	ZERO_BLANKING = 0 ;blank 1st digit zero (0 = no, 1 = yes)
.equ	FLASHING_COLON = 0 ;colon frequency (0 = static, 1 = 1 Hz, 2 = 0.5 Hz)
.equ	FLASH_SPEED = 100 ;Display flashing period (10 ms units), max. 255
.equ	BUTTON_SHORT_TIME = 2 ;Short button press (10 ms units), max. 255
.equ	BUTTON_LONG_TIME = 100 ;Long button press (10 ms units), max. 255
.equ	SET_TIMEOUT = 5*60*100 ;Timeout for set mode (10 ms units), max. 65535

;other settings
.equ	DIMMING = 1 ;display dimming (0=100%, 1=50%, 2=25%, 3=12.5%)
.equ	F_MUX = 500 ;display multiplexing frequency
.equ	F_CPU = 2000000 ;20 MHz / 10 = 2 MHz

;debug options
.equ	CRYSTAL_CHECK = 0 ;output F_XTAL / 64 on PA2 (display will be blank)

;PORTA
.equ	COLON = 1
.equ	SR_CK = 2
.equ	SR_D = 3
.equ	COM1 = 4
.equ	COM2 = 5
.equ	COM3 = 6
.equ	COM4 = 7

;PORTB
.equ	AC_IN = 0
.equ	BUTTON = 1

;===============================================================================

.macro shift_clock
	sbi	VPORTA_OUT, SR_CK
	cbi	VPORTA_OUT, SR_CK
.endmacro

.macro shift_bit
	sbrc	inttmp, @0
	sbi	VPORTA_OUT, SR_D
	sbrs	inttmp, @0
	cbi	VPORTA_OUT, SR_D
	shift_clock
.endmacro

;===============================================================================

.cseg
.org 0x000
	rjmp	reset
	
.org PORTB_PORT_vect
	;input edge interrupt (mains frequency input)
	rjmp	port_b

.org RTC_CNT_vect
	;RTC interrupt: AC fail detection & backup clock
	rjmp	rtc

.org TCA0_OVF_vect
	;TCA0 overflow (multiplexing)
	rjmp	ovf_a

;--------------------

port_b:
	in	sreg_backup, CPU_SREG
	sbrs	flags, fAcFailDetected
	rjmp	port_b_end
	sbis	VPORTB_IN, AC_IN
	rjmp	port_b_end
	;AC fail mode, rising edge
port_b_cnt:
	lds	inttmp, RTC_STATUS ;wait until CNT register has been updated
	sbrc	inttmp, RTC_CNTBUSY_bp
	rjmp	port_b_cnt
	movw	inttmp2:inttmp, last_ac_h:last_ac_l
	lds	last_ac_l, RTC_CNTL
	lds	last_ac_h, RTC_CNTH
	;out16
	com	inttmp2 ;subtract previous value from new value
	neg	inttmp
	brne	PC+2
	inc	inttmp2
	add	inttmp, last_ac_l
	adc	inttmp2, last_ac_h
	tst	inttmp2
	brne	port_b_fail ;way too much time between edges
	cpi	inttmp, 32768/8 * 5/4 / F_MAINS ;1.25 * T_AC
	brsh	port_b_fail ;too much time between edges
	cpi	inttmp, 32768/8 * 3/4 / F_MAINS ;0.75 * T_AC
	brlo	port_b_fail ;not enough time between edges
	;valid time between AC edges
	sbrs	ac_restore_cnt, 4 ;stop counting at 16
	inc	ac_restore_cnt
	sbrc	ac_restore_cnt, 4 ;consider AC restored after 16 edges
	ori	flags, 1<<fAcEdgesDetected
port_b_end:
	sbi	VPORTB_INTFLAGS, AC_IN ;clear interrupt flag
	out	CPU_SREG, sreg_backup
	reti
	
port_b_fail:
	;too much gap between "adjacent" AC edges, reset counter
	clr	ac_restore_cnt
	rjmp	port_b_end

;--------------------

rtc:
	;RTC overflow: AC fail detect or quartz back-up clock
	in	sreg_backup, CPU_SREG
	ldi	inttmp, RTC_OVF_bm
	sts	RTC_INTFLAGS, inttmp
	sbrs	flags, fAcFailDetected
	rjmp	rtc_ac_fail
	
	;RTC backup: increment time once per second
	rcall	inc_sec ;increment time by 1 second
	sbrs	flags, fAcEdgesDetected
	rjmp	rtc_end
	
	;AC power restored
rtc_ac_restored_per:
	lds	inttmp, RTC_STATUS
	sbrc	inttmp, RTC_PERBUSY_bp
	rjmp	rtc_ac_restored_per
	ldi	inttmp, LOW(32768/8 * 3/2 / F_MAINS - 1) ;period T = 1.5 * T_AC
	sts	RTC_PERL, inttmp
	ldi	inttmp, HIGH(32768/8 * 3/2 / F_MAINS - 1)
	sts	RTC_PERH, inttmp
	;if no phase shift occured between AC fail and AC restored, we should
	;be 1/2 * T_AC behind the rising edge of an AC pulse, so let's make
	;sure the input is low before detecting edges => set fAcState=1
	andi	flags, ~(1<<fAcEdgesDetected | 1<<fAcFailDetected)
	ori	flags, 1<<fAcRestored | 1<<fAcState
	clr	timeout
rtc_end:
	clr	ac_restore_cnt
	out	CPU_SREG, sreg_backup
	reti
	
rtc_ac_fail:
	;New AC fail detected
	;display off
	sts	PORTA_OUTCLR, mux
	nop ;NOTE: OUTCLR has no effect if followed by SBI/CBI. Silicon bug?
	sbi	VPORTA_OUT, COLON
	cbi	VPORTA_OUT, SR_D
	shift_clock ;1
	shift_clock ;2
	shift_clock ;3
	shift_clock ;4
	shift_clock ;5
	shift_clock ;6
	shift_clock ;7
	shift_clock ;8
	;stop TCA0 (multiplexing)
	ldi	inttmp, TCA_SINGLE_CLKSEL_DIV1_gc ;ENABLE = 0
	sts	TCA0_SINGLE_CTRLA, inttmp
	ldi	inttmp, TCA_SINGLE_OVF_bm
	sts	TCA0_SINGLE_INTFLAGS, inttmp
	;reconfgure RTC for 1 Hz periodic interrupt
rtc_ac_fail_per:
	lds	inttmp, RTC_STATUS
	sbrc	inttmp, RTC_PERBUSY_bp
	rjmp	rtc_ac_fail_per
	ldi	inttmp, LOW(32768/8 - 1)
	sts	RTC_PERL, inttmp
	ldi	inttmp, HIGH(32768/8 - 1)
	sts	RTC_PERH, inttmp
	;increment time to compensate for missed AC edge
	rcall	inc_time
	;set registers for battery backup mode
	andi	flags, ~(1<<fAcEdgesDetected)
	ori	flags, 1<<fAcFailDetected
	clr	set_digit ;immediately leave set mode
	clr	timeout
	rjmp	rtc_end

;--------------------

ovf_a:
	;interrupt for multiplexing
	in	sreg_backup, CPU_SREG
	ldi	inttmp, TCA_SINGLE_OVF_bm ;clear overflow flag
	sts	TCA0_SINGLE_INTFLAGS, inttmp
	
	;all digits off
	;NOTE: OUTCLR has no effect if followed by SBI/CBI. Silicon bug?
	sbi	VPORTA_OUT, COLON ;colon off
	sts	PORTA_OUTCLR, mux ;digit off
	
	;dimming
	inc	dim_cnt
	sbrs	dim_cnt, DIMMING
	rjmp	ovf_a_end
	clr	dim_cnt
	
	;update colon
.if (FLASHING_COLON == 1) ;1 Hz
	cpi	subsec, F_MAINS/2
	brsh	PC+2
.elif (FLASHING_COLON == 2) ;0.5 Hz
	sbrs	second, 0
.endif ;else: static (always on)
	cbi	VPORTA_OUT, COLON ;colon on
.if (FLASHING_COLON == 1) ;1 Hz
	cpi	subsec, F_MAINS/2
	brlo	PC+2
	sbi	VPORTA_OUT, COLON ;colon off
.elif (FLASHING_COLON == 2) ;0.5 Hz
	sbrc	second, 0
	sbi	VPORTA_OUT, COLON ;colon off
.endif ;else: static (always on)

	;find next digit
	ldi	inttmp, 1<<COM1
	lsl	mux
	brne	PC+2
	mov	mux, inttmp
	
	;load new data
	mov	inttmp, digit1
	sbrc	mux, COM2
	mov	inttmp, digit2
	sbrc	mux, COM3
	mov	inttmp, digit3
	sbrc	mux, COM4
	mov	inttmp, digit4
	
	;shift new data
	shift_bit 0
	shift_bit 1
	shift_bit 2
	shift_bit 3
	shift_bit 4
	shift_bit 5
	shift_bit 6
	shift_bit 7
	;bit 7 remains on the data output for segment i (always the same as h)
	
	;new digit on
	sts	PORTA_OUTSET, mux
	
	;decrement AC timeout
	tst	timeout
	breq	PC+2
	dec	timeout
	
	;divide to 100 Hz
	dec	intdiv
	brne	ovf_a_end
	ldi	inttmp, 4*F_MUX / 100
	mov	intdiv, inttmp
	
	;decrement set mode timeout
	cp	set_timeoutL, zero
	cpc	set_timeoutH, zero
	breq	set_timeout_end
	ldi	inttmp, 1
	sub	set_timeoutL, inttmp
	sbc	set_timeoutH, zero
	brne	set_timeout_end
	clr	set_digit ;exit set mode
set_timeout_end:

	;increment flashing counter
	inc	flash
	cpi	flash, FLASH_SPEED
	brlo	flash_end
	clr	flash
flash_end:

	;poll push-button
	sbic	VPORTB_IN, BUTTON
	rjmp	poll_button_released
	cpi	button_cnt, 0xFF
	breq	poll_button_end
	inc	button_cnt
	cpi	button_cnt, BUTTON_LONG_TIME
	brne	poll_button_end
	ori	flags, 1<<fButtonLong
	rjmp	poll_button_end
poll_button_released:
	cpi	button_cnt, BUTTON_SHORT_TIME
	brlo	poll_button_short_end
	cpi	button_cnt, BUTTON_LONG_TIME
	brsh	poll_button_short_end
	ori	flags, 1<<fButtonShort
poll_button_short_end:
	clr	button_cnt
poll_button_end:

ovf_a_end:
	out	CPU_SREG, sreg_backup
	reti

;===============================================================================

reset:
	;init ports
	ldi	temp, 1<<COLON ;Colon off
	out	VPORTA_OUT, temp
	ldi	temp, 0xFF ;PORTA: all outputs
	out	VPORTA_DIR, temp
	ldi	temp, 0x00 ;PORTB: all inputs
	out	VPORTB_DIR, temp
	;NOTE: must use BOTHEDGES (or LEVEL) to wake from STANDBY mode
	ldi	temp, PORT_ISC_BOTHEDGES_gc ;both edges interrupt on ...
	sts	PORTB_PIN0CTRL, temp ;PB0 f_in
	ldi	temp, PORT_PULLUPEN_bm ;enable pull-up on ...
	sts	PORTB_PIN1CTRL, temp ;PB1 button
	ldi	temp, PORT_ISC_INPUT_DISABLE_gc ;disable input buffer on ...
	sts	PORTB_PIN2CTRL, temp ;PB2 XTAL
	sts	PORTB_PIN3CTRL, temp ;PB3 XTAL
	
	;set clock divider: 20 MHz (selected by fuses) / 10 = 2 MHz
	ldi	temp, CPU_CCP_IOREG_gc ;enable write to protected I/O register
	out	CPU_CCP, temp
	ldi	temp, CLKCTRL_PDIV_10X_gc | CLKCTRL_PEN_bm ;Clk/10
	sts	CLKCTRL_MCLKCTRLB, temp
	
	;init RTC (used for battery backup timekeeping)
	ldi	temp, CLKCTRL_CSUT_32K_gc ;start-up time = 32k cycles
	sts	CLKCTRL_XOSC32KCTRLA, temp
	ldi	temp, CPU_CCP_IOREG_gc ;enable write to protected I/O register
	out	CPU_CCP, temp
	ldi	temp, CLKCTRL_CSUT_32K_gc | CLKCTRL_RUNSTDBY_bm | CLKCTRL_ENABLE_bm
	sts	CLKCTRL_XOSC32KCTRLA, temp ;enable XOSC32
	ldi	temp, RTC_CLKSEL_TOSC32K_gc ;select XOSC32 for RTC
	sts	RTC_CLKSEL, temp
xtal_init_wait:
	lds	temp, CLKCTRL_MCLKSTATUS ;wait until XOSC32 is stable
	sbrs	temp, CLKCTRL_XOSC32KS_bp
	rjmp	xtal_init_wait
rtc_init_wait:
	lds	temp, RTC_STATUS
	andi	temp, RTC_PERBUSY_bm | RTC_CTRLABUSY_bm
	brne	rtc_init_wait
	ldi	temp, LOW(32768/8 * 3/2 / F_MAINS - 1) ;period T = 1.5 * T_AC
	ldi	temp2, HIGH(32768/8 * 3/2 / F_MAINS - 1)
	sts	RTC_PERL, temp
	sts	RTC_PERH, temp2
	ldi	temp, RTC_RUNSTDBY_bm | RTC_PRESCALER_DIV8_gc | RTC_RTCEN_bm
	sts	RTC_CTRLA, temp ;Clk/8 = 4096 Hz
	ldi	temp, RTC_OVF_bm ;enable overflow interrupt
	sts	RTC_INTCTRL, temp
	
.if (CRYSTAL_CHECK)
	;output crystal frequency on PA2 (expected: 512 Hz)
	ldi	temp, EVSYS_ASYNCCH3_PIT_DIV64_gc
	sts	EVSYS_ASYNCCH3, temp
	ldi	temp, EVSYS_ASYNCUSER8_ASYNCCH3_gc
	sts	EVSYS_ASYNCUSER8, temp
	ldi	temp, PORTMUX_EVOUT0_bm
	sts	PORTMUX_CTRLA, temp
	rjmp	PC
.endif
	
	;init TCA0 (used for multiplexing & button polling)
	ldi	ZL, LOW(TCA0_base)
	ldi	ZH, HIGH(TCA0_base)
	;Period: F_CPU / (4 digits * F_MUX * 2^DIMMIMG)
	ldi	temp, LOW(F_CPU/(4*F_MUX*(1<<DIMMING)) - 1)
	ldi	temp2, HIGH(F_CPU/(4*F_MUX*(1<<DIMMING)) - 1)
	std	Z+TCA_SINGLE_PER_offset, temp
	std	Z+TCA_SINGLE_PER_offset+1, temp2
	ldi	temp, TCA_SINGLE_OVF_bm ;enable overflow interrupt
	std	Z+TCA_SINGLE_INTCTRL_offset, temp
	ldi	temp, TCA_SINGLE_CLKSEL_DIV1_gc | TCA_SINGLE_ENABLE_bm ;Clk/1
	std	Z+TCA_SINGLE_CTRLA_offset, temp
	
	;init registers
	clr	zero
	clr	set_digit
	clr	flags
	clr	flash
	clr	mux
	clr	button_cnt
	clr	timeout
	clr	set_timeoutL
	clr	set_timeoutH
	clr	ac_restore_cnt
	clr	intdiv
	clr	subsec
	clr	second
	clr	minute
	clr	hour
	clr	digit1
	clr	digit2
	clr	digit3
	clr	digit4
	clr	dim_cnt
	
	;enable interrupts
	sei
	
;-------------------------------------------------------------------------------
	
loop:

	;check AC input
	sbrc	flags, fAcState
	rjmp	ac_falling
	;waiting for rising edge
	sbis	VPORTB_IN, AC_IN
	rjmp	ac_end
	ori	flags, 1<<fAcState
	ldi	timeout, 4*F_MUX * 3 / (4 * F_MAINS) ;3/4 of period
	;increment time
	rcall	inc_time
	;reset mains fail timer
ac_wait:
	lds	temp, RTC_STATUS
	sbrc	temp, RTC_CNTBUSY_bp
	rjmp	ac_wait
	sts	RTC_CNTL, zero
	sts	RTC_CNTH, zero
	rjmp	ac_end
	
ac_falling:
	;waiting for falling edge
	tst	timeout
	brne	ac_end
	sbic	VPORTB_IN, AC_IN
	rjmp	ac_end
	andi	flags, ~(1<<fAcState)
	;ldi	timeout, 4*F_MUX / (2 * F_MAINS) ;1/2 of period (total: 5/4)
ac_end:

	;check for AC fail
	sbrs	flags, fAcFailDetected
	rjmp	ac_fail_end
	;AC fail detected: sleep
	sbi	VPORTA_OUT, COLON
	ldi	temp, SLPCTRL_SMODE_STDBY_gc | SLPCTRL_SEN_bm
	sts	SLPCTRL_CTRLA, temp
ac_fail_sleep:
	sleep
	sbrs	flags, fAcRestored
	rjmp	ac_fail_sleep
	;AC edge detected
	;restart multiplexing
	ldi	temp, TCA_SINGLE_CLKSEL_DIV1_gc | TCA_SINGLE_ENABLE_bm ;Clk/1
	sts	TCA0_SINGLE_CTRLA, temp
	andi	flags, ~(1<<fAcFailDetected | 1<<fAcRestored)
ac_fail_end:

	;check buttons
	sbrc	flags, fButtonShort
	rcall	button_short
	sbrc	flags, fButtonLong
	rcall	button_long
	
	;update hours display
	mov	temp, hour
.if (ZERO_BLANKING)
	cpi	temp, 0x10
	brsh	PC+2
	ori	temp, 0xA0
.endif
	rcall	convert
	;flashing digits when setting time
	cpi	set_digit, 1
	sbrc	flags, fTimeSet
	brne	set_h_end
	cpi	flash, FLASH_SPEED/2
	brlo	set_h_end
	clr	temp
	clr	temp2
set_h_end:
	mov	digit1, temp
	mov	digit2, temp2
	
	;update minutes display
	mov	temp, minute
	rcall	convert
	;flashing 10s digit when setting time
	cpi	set_digit, 2
	sbrc	flags, fTimeSet
	brne	set_m10_end
	cpi	flash, FLASH_SPEED/2
	brlo	set_m10_end
	clr	temp
set_m10_end:
	;flashing 1s digit when setting time
	cpi	set_digit, 3
	sbrc	flags, fTimeSet
	brne	set_m1_end
	cpi	flash, FLASH_SPEED/2
	brlo	set_m1_end
	clr	temp2
set_m1_end:
	mov	digit3, temp
	mov	digit4, temp2
	
	rjmp	loop
	
;===============================================================================

button_short:
	;short button press
	andi	flags, ~(1<<fButtonShort)
	ldi	flash, 0
	cpi	set_digit, 1
	breq	adj_h1
	cpi	set_digit, 2
	breq	adj_m10
	cpi	set_digit, 3
	breq	adj_m1
	;not in set mode: toggle summer/winter time
	sbrs	flags, fTimeSet
	ret
	ldi	temp, 1<<fDST
	eor	flags, temp
	sbrc	flags, fDST
	rjmp	inc_hour ;winter -> summer: increment hour
	;summer -> winter: decrement hour
	subi	hour, 1
	brcs	dst_h23 ;hour wrapped around from 0 to 23
	brhc	PC+2
	subi	hour, 6
	ret
	
dst_h23:
	ldi	hour, 0x23
	ret
	
adj_h1:
	subi	hour, -7
	brhc	PC+2
	subi	hour, 6
	cpi	hour, 0x24
	brlo	PC+2
	clr	hour
	rjmp	restart_set_timeout

adj_m10:
	clr	subsec
	clr	second
	mov	temp, minute
	andi	temp, 0xF0
	subi	temp, -0x10
	cpi	temp, 0x60
	brlo	PC+2
	clr	temp
	andi	minute, 0x0F
	or	minute, temp
	rjmp	restart_set_timeout
	
adj_m1:
	clr	subsec
	clr	second
	mov	temp, minute
	andi	temp, 0x0F
	inc	temp
	cpi	temp, 0x0A
	brlo	PC+2
	clr	temp
	andi	minute, 0xF0
	or	minute, temp
	rjmp	restart_set_timeout
	
;--------------------
	
button_long:
	;long button press
	andi	flags, ~(1<<fButtonLong)
	ori	flags, 1<<fTimeSet
	inc	set_digit
	andi	set_digit, 0x03
	ldi	flash, FLASH_SPEED/2 ;digit off immediately
restart_set_timeout:
	ldi	temp, LOW(SET_TIMEOUT)
	ldi	temp2, HIGH(SET_TIMEOUT)
	movw	set_timeoutH:set_timeoutL, temp2:temp
	ret

;===============================================================================

inc_time:
	;increment time
	inc	subsec
	cpi	subsec, F_MAINS
	brlo	inc_time_end
	clr	subsec
inc_sec:
	inc	second ;second
	cpi	second, 60
	brlo	inc_time_end
	clr	second
	subi	minute, -7 ;minute
	brhc	PC+2
	subi	minute, 6
	cpi	minute, 0x60
	brlo	inc_time_end
	clr	minute
inc_hour:
	subi	hour, -7 ;hour
	brhc	PC+2
	subi	hour, 6
	cpi	hour, 0x24
	brlo	inc_time_end
	clr	hour
inc_time_end:
	ret
	
;--------------------

convert:
	;convert packed BCD 'temp' to two segmented digits 'temp' and 'temp2'
	mov	temp2, temp
	andi	temp2, 0x0F
	swap	temp
	andi	temp, 0x0F
	ldi	ZL, LOW(numerals*2)
	ldi	ZH, HIGH(numerals*2)
	add	ZL, temp
	ldi	temp, 0
	adc	ZH, temp
	lpm	temp, Z
	ldi	ZL, LOW(numerals*2)
	ldi	ZH, HIGH(numerals*2)
	add	ZL, temp2
	ldi	temp2, 0
	adc	ZH, temp2
	lpm	temp2, Z
	ret

numerals:
	;bits: [ih g f e . d c b a]
	;     0     1     2     3     4     5     6     7     8     9   blank
	.db 0x1c, 0x80, 0x1b, 0x0f, 0xe0, 0x2d, 0x1e, 0x13, 0x3f, 0x33, 0x00, 0